Abstract
Much design effort toward a Sproull Counterflow Pipeline Processor has been focused on management of movements of Instructions and Results in the pipelines so that every Instrucion and Result that pass one another meet and interact in exacly one stage of the pipeline. The full SCPP design problem poses other requirements as well, such as creation and deletion of items flowing in the pipelines, scheduling of execution of instructions only in stages with the required hardware, and high speed.
Nevertheless, even a simplified version of the design problem that ignores the latter requirements has resisted synthesis using existing formal methods. At a workshop on Asynchronous VLSI Design held in ISrael on March 20-22, 1995, Alain Martin of Caltech discussed his synthesis methodology and tools, which he claimed can translate almost any Communicating Sequential Process (CSP) program to a circuit by systematic procedure. Since our essential requirements for movement of Instructions and Results had been expressed by us as a 5-state FSM graph that is easily interpreted as a CSP program, we asked Martin to demonstrate how his method would be applied to this problem.
At the suggestion of the workshop organizer, Dr. Ran Ginosar if the Technion, Dr. Huub Schols presented the challenge to all workshop attendees, and produced the careful documentation cantained here. Several thoughtful responces to our challenges are cited in the list of references. They lead us to conclude that the problem that we have posed is indeed difficult and worthy of further study and analysis.
Martin has declined to provide us with any information about a solution that he claimed to have found after the workshop.
