The Center for Education and Research in Information Assurance and Security (CERIAS)

The Center for Education and Research in
Information Assurance and Security (CERIAS)

Why Wire Delays Will No Longer Scale for VLSI Chips

Author

Neil C. Wilhelm

Entry type

techreport

Abstract

Past scaling of VLSI circuits has resulted in wire delays that scale as the square factor. This has occurred because wires have been much wider than they are thick: their aspect ratio has been (much) greater than one. For today's and future VLSI processes, the aspect ratio of wires will be very near to one, and scaling will no longer produce dramatic decreases i wire delays. Long wires will gain the least from future scaling suggesting that, more than ever, high-speed system designs will have to avoid long-distance communiation.

Date

1995

Address

Mountain View, CA, USA

Key alpha

Wilhelm

Publisher

Sun Microsystems Laboratories

Affiliation

Sun Microsystems Laboratories

Publication Date

1995-00-00

Contents

1 Introducion 2 Scaling in VLSI Processes 3 Aspect Ratio Scaling 4 Scaling in the Future 5 How Capacitance Varies with Aspect Ratio 6 How the RC Product Varies with Aspect ratio 7 the Future of Wire Delays 8 Conclusion

Copyright

1995

Language

Englsh

Location

A hard-copy of this is in the Papers Cabinet

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