Robert F. Sproull, Ivan E. Sutherland, Charles E. Molnar

article

The counterflow pipeline processor architecture (CFPP) is a proposal for a family of microarchitectures for RISC processors. The architecture derives from its fundamental features, namely that is=nstructions and results flow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signal, and simplicity that might lead to provably correct processor designs. Moreover, CFPP designs allow asynchronous implementations, in conventional pipeline designs where the synchronization required for operand forwarding makes asynchronouw designs unattractive. This paper presents the CFPP architecture and a proposal for an asynchronous implementation. Details performance simulations of a complete processor design are not yet available.

1994

Mountain View, CA, USA

IEEE Design & Test of Computers

Sproull

3

Institute of Electrical and Electronics Engineers

Sun Microsystems Laboratories

11

Sun Microsystems Laboratories

1994-00-00

1 Introduction 2 Basic Structure 3 Pipeline Rules 4 An Example 5 Traps and Conditional Branches 6 Function Units and sidings 7 register Files and register Caches 8 Implementations 9 Discussion

1994

processor design, RISC architecture, micropipelines, FIFO, asynchronous systems

English

A hard-copy of this is in the Papers Cabinet